######################################################################################################## ## _______ _ __ __ _ ## / ___/ / (_)__ __ _ __ _____ / /__ / / ___ ___ _(_)___ TM ## / /__/ _ \/ / _ \/ ' \/ // / _ \/ '_/ / /__/ _ \/ _ `/ / __/ // O P E N - S O U R C E // ## \___/_//_/_/ .__/_/_/_/\_,_/_//_/_/\_\ /____/\___/\_, /_/\__/ ## /_/ /___/ chipmunklogic.com ######################################################################################################## +------------------------------------------------------------------------------------------------------+ | BUILD, COMPILE, SIMULATE, SYNTHESIS NOTES | +------------------------------------------------------------------------------------------------------+ | The PQR5 database integrates a comprehensive Makefile-based toolchain for end-to-end build | automation and flow control. | | REQUIREMENTS/DEPENDENCIES | ========================= | 1) Linux OS/Windows OS with bash shell emulator like MSYS/GitBash | 2) GNU Make utility | 3) TCL support | 4) Python support, atleast 3.9 | 5) RISC-V GCC (14.2.0 tested, newlib) | 6) Compilation & Simulation flow is compatible with latest ModelSim/QuestaSim | 7) Synthesis, Implementation, & Bitfile generation flow is compatible with Xilinx Vivado | 8) PQR5 tool suite: pqr5asm (Assembler), peqFlash (Flasher), helper scripts | | STEPS to build a sample PQR5 SUBSYSTEM with Firmware | ==================================================== | 1) Compile any ASM program in assembler/example_programs: | >> make asm2bin ASM=01_test_regfile.s ASMF=<> | | This will generate the binaries (raw & ASCII hex text) in assembler/ | | 2) Generate IRAM and DRAM which is initialized on power-on (on FPGAs) with binaries from (1): | >> make genram ISZ=8192 DSZ=4096 OFT=<> | | This will generate a synthesisable IRAM & DRAM model of 8kB and 4kB, with first instruction | copied at address: 0x0000_0000 ... All memory files are generated in src/memory | | NOTE: In case Assembler compiled & generated a non-relocatable binary: | -- OFT should be same as .org address in the text section of ASM program. | -- PC_INIT parameter of PQR5 Core should be the same address to boot the Subsystem | correctly. | In case Assembler compiled & generated a relocatable binary code (with ASMF=-pcrel): | -- OFT may not necessarily be the same as .org address. | -- OFT and PC_INIT should be the same. | By default, Makefile generates relocatable binary code with ASMF=-pcrel | | 3) Configure PQR5 Core and Subsystem macros in src/include/ for RTL elaboration & simulation | | 4) Compile PQR5 Core and Subsystem with the generated memory models | >> make compile | | 5) The processes in (1, 2, 4) can also be combined by running "build": | >> make build ASM=01_test_regfile.s ISZ=8192 DSZ=4096 OFT=<> | | 6) Configure scripts/run.do if reqd for simulation specific commands | | 7) Run PQR5 Subsystem simulation with firmware: | >> make sim GUI=<> | | Find all simulation dumps in dump/ | Find all logs in sim/ | | 8) To configure the subsystem for synthesis, SYNTH macros should be set before compilation | and synthesis. | | 9) Steps for synthesis and programming bitfile with Vivado for Xilinx FPGAs | a) Build the synth setup in Vivado by running: make build_synth | b) Make target-specific changes to the spawned RTL source files in synth/rtl_src if required | This includes setting SYNTH MACROs, test env & design MACROs, configure I/O ports etc | c) Create a top-level XDC constraints file for the design in synth/ | d) Configure the TCL scripts in synth/ | e) Run synthesis by running: make_synth | This will run synthesis + implementation + generation of bitfile | f) Verify all the outputs, reports & logs in synth/*_outputs, check errors/warnings, if any | g) Burn the bitfile to the target FPGA by running: make burn | | 10) Steps to flash the program binary to target | a) Make sure PQR5 subsystem is synthesised and implemented with Loader | b) Generate the bitstream and send to the target | c) Invoke peqFlash to flash the program binary by running: make flash | | | Running Regressions in the CPU | =============================== | Running regressions validate the functionality of the PQR5 subsystem built. | This will run all example programs in the CPU and dump the results in dump/regress_run_dump. | | Following configuration should be set before running regression. | | PQR5 subsystem macros: | . IRAM_SIZE = 1024 | . DRAM_SIZE = 1024 | . SUBSYS_DBG = Enable | . MEM_DBG = Enable | . SIMLIMIT = Enable | CPU core macros: | . PC_INIT = 32'h00000000 | . REGFILE_DUMP = 1 | . SIMLIMIT = Enable | . SIMEXIT_INSTR_END = Enable | | Run regressions: make regress | | | Building CoreMark® CPU Benchmark | ================================ | Steps to compile CoreMark and build the Pequeno subsystem with the CoreMark binaries | initialized on RAMs. | | STEPS | ----- | 1) Configure the test parameters and environment in coremark/Makefile. | . ITERATIONS = | . CLOCKS_PER_SEC = | | 2) Configure coremark/linker.ld. | . IRAM ORIGIN = 0x00000000 | . IRAM LENGTH = | . DRAM ORIGIN = 0x80000000" | . DRAM LENGTH = | | 3) Configure the PQR5 subsystem macros: | . COREMARK = Enable | . DBGUART = Enable | . DBGUART_BRATE = | . FCLK = CLOCKS_PER_SEC | . IRAM_SIZE = IRAM LENGTH | . DRAM_SIZE = DRAM LENGTH | . SUBSYS_DBG = Enable if RTL simulation required | | 4) Configure CPU core macros: | . PC_INIT = 0x00000000 | . SIMEXIT_INSTR_END = Enable if you require RTL simulation with exit on END | | 5) Run CoreMark: make coremark ISZ= DSZ= | | 6) After successful compilation, the design can be simulated or synthesised for on-board. | At the end of the execution of all iterations of CoreMark, a benchmark report is generated, | which is serially sent through the Debug UART. Serial terminal is required to view this report. | Please note that simulation can be slow and produces no dump. | | | NOTE: run "make help" to understand the full list of Makefile recipes & parameters | +------------------------------------------------------------------------------------------------------+ | C H I P M U N K L O G I C ™ chipmunklogic.com | +------------------------------------------------------------------------------------------------------+