Serial Peripheral Interface Reusable Driver (Master-Slave) v1.1
This project implements SPI reusable driver that can be adapted to various microcontrollers.
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Serial Peripheral Interface (Master-Slave) Reusable Driver - Version 1.1

Table of Contents

Introduction

This project is a personal initiative aimed at developing reusable firmware components for microcontroller platforms. It focuses on building a modular and efficient SPI (Serial Peripheral Interface) driver that facilitates communication between two STM32 Nucleo-F401RE boards configured in a Master-Slave setup. The DIO driver is used to configure the selected SPI pins and establish the necessary physical connections.

Version History

  • v1.0: Initial release.
  • v1.1: Updated documentation, structural improvements, and design by contract enhancements.

Software Architecture Overview

The software architecture follows a layered approach. This design pattern separates low-level driver code (HALs) from application-specific code, promoting reusability and simplifying portability between different applications or microcontrollers. The layered architecture can be seen in figure 1 and contains a driver and application layer operating on the hardware.

Application Code
Drivers
Hardware
Figure 1. Two-Layer Software Architecture.

The Driver Layer includes all code required to initialize and control microcontroller peripherals.
The Application Layer uses these drivers to implement the program logic, keeping hardware interactions abstracted and maintainable.

Coding Standards

This firmware is developed using a bare-metal approach and adheres to the MISRA-C guidelines. Standardized naming, consistent formatting, modular design, and structured documentation practices are followed throughout the project.

Project Description

This setup uses two STM32 Nucleo-F401RE boards: one as SPI master, and the other as SPI slave.
The configuration includes:

  • SPI Channel: SPI1 on both devices.
  • Baud Rate: 4 kHz.
  • Communication: Full duplex.
  • Data Frame: 8-bit.
  • Bit Order: MSB first.

The GPIO (DIO) driver configures the pin mappings, as shown in the table below:

SPI Connection Master Slave Logic Analyzer
NSS PA4 PA4 CH4
SCK PA5 PA5 CH1
MISO PA6 PA6 CH2
MOSI PA7 PA7 CH3
Table 1. SPI Pin Connections.

Operation Summary:

  • The slave device continuously sends the byte 0x66 to the master.
  • The master receives this value and echoes it back to the slave.
  • The KY-57 logic analyzer is connected to monitor this SPI exchange in real-time.

Project Requirements

  • Develop a reusable SPI master-slave communication driver.
  • Ensure compatibility and portability across STM32 and other microcontrollers.
  • Comply with professional firmware development practices (MISRA-C).

Development Tools

  • Development Board: STM32 Nucleo-F401RE.
  • IDE/Debugger: Visual Studio Code with PlatformIO extension.
  • Toolchain: GNU ARM Embedded Toolchain.

Usage & Documentation

The codebase is thoroughly documented using Doxygen, with inline comments detailing the logic and configuration of each module. The generated documentation provides an intuitive, navigable interface to explore API details and implementation specifics.

Glossary

  • SPI: Serial Peripheral Interface.
  • DIO: Digital Input/Output.