Serial Peripheral Interface Reusable Driver v1.1
This project implements SPI reusable driver that can be adapted to various microcontrollers.
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Serial Peripheral Interface (SPI) Reusable Driver - Version 1.1

Table of Contents

Introduction

This project is a personal initiative aimed at developing reusable firmware components for microcontroller platforms. It focuses on creating a modular and efficient Serial Peripheral Interface (SPI) driver that can be easily adapted across various microcontroller families. The DIO driver is utilized to configure the selected SPI port for physical connectivity.

Version History

  • v1.0: Initial release.
  • v1.1: Updated documentation, structural improvements, and design by contract enhancements.

Software Architecture

The software architecture follows a layered approach. This design pattern separates low-level driver code (HALs) from application-specific code, promoting reusability and simplifying portability between different applications or microcontrollers. The layered architecture can be seen in figure 1 and contains a driver and application layer operating on the hardware.

Application Code
Drivers
Hardware
Figure 1. Two-Layer Software Architecture.

The Driver Layer includes all necessary low-level code to initialize and manage hardware peripherals like SPI modules.
The Application Layer contains no hardware-specific code but instead interacts with the hardware through the driver interfaces, ensuring abstraction and easier maintenance.

Coding Standards

This project is developed as bare-metal firmware and adheres to industry-standard coding practices, specifically the MISRA-C guidelines.
Best practices such as consistent naming conventions, clear code formatting, modularity, and detailed documentation are followed throughout.

Project Description

This demonstration configures the SPI1 peripheral as a master device with the following settings:

  • Baud rate: 4 kHz.
  • Communication: Full duplex.
  • Data frame format: 8 bits.
  • Bit order: Most Significant Bit (MSB) first.

The physical connections between the STM32 Nucleo board and the KY-57 logic analyzer are configured using the DIO driver and follow this mapping:

SPI Connection Master Logic Analyzer
NSS PA9 CH4
SCK PA5 CH1
MISO PA6 CH2
MOSI PA7 CH3
Table 1. SPI Pin Connections.

During operation, the master continuously transmits the data byte 0x56 to the KY-57 logic analyzer for capture and analysis.

Project Goals

  • Provide a reusable, modular SPI driver for embedded applications.
  • Maintain portability across different microcontroller platforms.
  • Follow industry-standard coding guidelines (MISRA-C) for reliability and maintainability.

Development Tools

  • Development Board: STM32 Nucleo-F401RE.
  • IDE/Debugger: Visual Studio Code with PlatformIO extension.
  • Toolchain: GNU ARM Embedded Toolchain.

Usage & Documentation

The project is fully documented using Doxygen.
Extensive inline comments provide insights into the functionality, assumptions, and limitations of the code.
The Doxygen-generated documentation offers a structured and easy-to-navigate reference for developers.

Glossary

  • SPI: Serial Peripheral Interface.
  • DIO: Digital Input/Output.